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CPC5710N
Phone Line Monitor (PLM) IC
Features
* Excellent common-mode rejection ratio (CMRR), >40 dB * Supplied application circuits can meet isolation requirements of worldwide telephony standards * Small 8-pin SOIC * Worldwide telephone network compatibility * Full-wave ringing level detector comparator with internal threshold, large hysteresis, and logic-level output * 3.3 or 5.0 Volt operation * High differential input impedance, very low commonmode input impedance * Fixed gain * Differential or single-ended linear output * TTL logic input * CMOS logic output (TTL compatible) * Virtually non-detectable in voice monitoring applications
Description
The Clare CPC5710N is a CMOS special purpose fixed-gain amplifier with comparator for telephone line monitoring. The high (>40 dB) common-mode rejection ratio makes the CPC5710N an excellent choice for signal monitoring, discrete voice recording, and line condition monitoring applications. The CPC5710N is ideal for modem applications including embedded modem designs like set-top boxes, and voice recording applications.
Ordering Information
Part Number CPC5710N CPC5710NTR Description Phone line monitor IC, tubed Phone line monitor IC, tape and reel
Applications
* In signal monitoring applications, CPC5710N can be used for: * Display feature (caller ID) signal processing * Line-in-use detection (another-phone-off-hook) * Ringing signal level detection * Battery presence monitoring * Tip and ring lead voltage monitoring * Line condition detection, including line polarity, tip and ring lead voltage, and battery presence Figure 1. CPC5710N Block Diagram
3 LIN/CMP 1.625 V VDD + 6 7 ININ+ 0V AV=6 2V LINOUT4 LINOUT+ 5 + CMPOUT 2 VDD VDD 1
VSS
+ 1.25 V VSS
VSS
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DS-CPC5710-R1.0 12/16/2002
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CPC5710N
1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Environmental Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Another-Phone-Off-Hook (APOH) and Line Polarity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Non-Intrusive Line Monitoring, Display Feature (Caller ID) Signal Reception, and Ring Detection Application . . . . . . . . . . . . . . . . 2.2.1 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Regulatory Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Using CPC5710N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 LIN/CMP Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Amplifier Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Linear Amplifier Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Comparator Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Ringing Signal Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Setting Ring Detection Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 4 4 5 5 6 6 6 7 7 7 7 7 7 7
4 Power Quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 8 8 9
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Rev. 1.0 12/16/2002
CPC5710N
1. Specifications
1.1 Absolute Maximum Ratings
Parameter VDD Storage temperature Total package power dissipation Logic input voltage -0.3 Minimum Maximum -0.3 -40 6 +125 300 VDD + 0.3 Unit V C mW V
Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability.
1.2 Electrical Characteristics
VDD = 5V, temperature = 25 C unless otherwise indicated.
Parameter DC Characteristics Supply voltage, VDD Supply current, IDD AC Characteristics Input Impedance Input offset voltage, VIO Input offset current, IIO Input offset current. IIO Output DC bias level Output Low Voltage Swing Gain, AV Common-mode rejection ratio, CMRR Equivalent input noise voltage, VN
Conditions
Minimum
Typical
Maximum
Unit
3.0 -
-
5.5 10
V mA
10 No common-mode signal applied With 12 A of common-mode signal applied At LINOUT+ or LINOUT-, IO @ 0.5 mA IO = 0.5 mA 0 to 20 kHz Using supplied application circuits, with common-mode current 12 A, 0 to 120 Hz 0.9 5.88 40 -
1.0 6 -90
40 35 125 1.1 50 6.12 -
M mV nA nA V mV dB dBm/Hz
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CPC5710N
Parameter Comparator Threshold Characteristics Comparator detection threshold voltage Comparator detection threshold voltage Comparator hysteresis voltage ICM = 0 ICM = 12 A ICM = 0 675 488 300 750 750 375 850 1012 450 mV mV mV Conditions Minimum Typical Maximum Unit
LIN/CMP Input Characteristics Input low voltage Input high voltage Input high leakage current (IIH) Input low leakage current (IIL) VIL VIH VIH = 2.4 V VIL = 0.4 V 2.0 0.8 -120 -120 V V A A
Unless otherwise specified, minimum and maximum values are production testing requirements. Typical values are characteristic of the device and are the result of engineering evaluations. Typical values are provided for information purposes only and are not part of the testing requirements.
1.3 Environmental Characteristics
Parameter Operating temperature Operating humidity non-condensing Conditions Minimum -40 5 Typical Maximum +85 95 Unit C %
1.4 Pinout
Pin 1 2 3 4 5 6 7 8 Name VDD CMPOUT LIN/CMP LINOUTLINOUT+ IN+ INVSS Power supply Comparator output, active low Output select, low for linear output or high for comparator output Negative differential linear output Positive differential linear output Positive differential input Negative differential input Ground Description
Figure 2. Package Pinout
1 2 3 4 VDD CMPOUT VSS ININ+ 8 7 6 5
LIN/CMP LINOUT-LINOUT+
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CPC5710N
2. Applications
2.1 Another-Phone-Off-Hook (APOH) and Line Polarity Detector
This circuit performs two additional phone line interface functions, APOH and line polarity detection. The APOH output is logic low if another phone connected in parallel to the detector is off-hook, specifically, if the tip lead to ring lead voltage is less than approximately 18 V. The polarity output indicates the polarity of the phone line. If tip is positive with respect to ring, polarity out will be high.
Figure 3. APOH and Polarity Detection Application Circuit
+V
U1 CPC5710
VDD LIN/CMP A 1.625 V VDD R1-4 8.06 M 1% EIA 1206 + R5 604 K IN+ 0V AV=6 2V LINOUT+ + CMPOUT VDD
+V
R14 4.7 M
R16 10 K
R13 20 K IN+
1/4 U2 LM339 OUT
Polarity OUT
+V R15 10 K
INR17 4.7 M R12 20 K IN+ R11 499 K R10 21 K R8 20 K R9 499 K INA IN+ + 1.25 V VSS R7 21 K VSS 1/4 U2 LM339 OUT LINOUTINR6 4.7 M 1/4 U2 LM339 OUT
TIP
RING
IN-
VSS
APOH OUT
C1 1 nF A
Unless noted otherwise: All resistors 1%, 1/16 W. All capacitors 16 V 10%.
A
A
Rev. 1.0 12/16/2002
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CPC5710N 2.2 Non-Intrusive Line Monitoring, Display Feature (Caller ID) Signal Reception, and Ring Detection Application
This application uses the logic input LIN/CMP to select between detecting ringing or passing through display feature (caller-ID) and voice signals. Note the AC coupling of the tip and ring signals. With this circuit, set LIN/CMP high to detect ringing. After a valid ring, set LIN/CMP low to couple the audio channel signal to the output pins. Please see "Comparator Considerations" on page 7 for more information on ringing detection.
Figure 4. Non-Intrusive Line Monitoring, Display Feature (Caller ID) Signal Reception, and Ring Detection Application Circuit
3.3 or 5 V From Control Logic
U1 CPC5710
VDD LIN/CMP 1.625 V VDD R1-4 (RSNP) 1.8 M R5 (RSNPD) C1,2 (CSNP) 1.5 M, 1% 220 pF 0603 + IN+ 0V AV=6 2V LINOUT+ Display Feature Output VOUT = VIN at 500 Hz + CMPOUT VDD RING DETECT (to ring parser)
TIP
RING
IN-
LINOUT-
VSS
+ 1.25 V VSS
VSS
Unless noted otherwise: All resistors are 1/8 W, 1%, 1206. All capacitors are 2 kV, 10%.
A
2.2.1 Frequency Response
The blocking capacitors used in this application circuit affect the frequency response of the system. With the components shown, response rolls off 3 dB @ 166 Hz. Other values can be used for different response characteristics.
2.3 Regulatory Issues
Component sizing and value recommendations shown in the application circuits above will need to be reviewed with regard to the regulatory requirements of any particular application.
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CPC5710N
3. Using CPC5710N
3.1 LIN/CMP Input
The LIN/CMP input selects the active output, either the comparator output CMPOUT or the linear outputs, LINOUT- and LINOUT+. Set LIN/CMP low for linear output and high for comparator output. Note that both outputs cannot be used at once. With LIN/CMP at logic low (LIN/CMP = 0), the amplifier outputs are biased at 1 Vdc and CMPOUT is held high. With LIN/CMP at logic high (LIN/CMP = 1), LINOUT+ is 0 V and LINOUT- is 2 V.
6R SNPD GAIN CID ( dB ) = 20 log ---------------------------------------------------------------------------------------2 1 ( 4R +R ) + ------------------------SNP SNPD
( fC SNP )
2
where is the frequency of the signal. Clare Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this type of circuit.
Figure 5. LIN/CMP Timing for Caller-ID Signal Reception
2s 500 ms 3s 475 ms 2s
3.3 Comparator Considerations
3.3.1 Ringing Signal Detection
The CPC5710N comparator is a full-wave configuration. Ringing signals will assert the output on positive and negative parts of the ringing waveform. Hysteresis is employed in the internal comparator circuit to provide noise immunity. The set-up of the comparator causes CMPOUT output pulses to remain low for most of the ringing signal positive and negative half-cycles. CMPOUT returns high when the ringing signal is near the zero-voltage crossing.
Caller ID data
LIN/CMP
Signal levels not to scale
Figure 6. CMPOUT Relative to Ring Signal
3.2 Amplifier Design Considerations
Amplifier inputs are biased at 1.25 Vdc, the internal voltage references. The internal common-mode circuitry maintains the average of the inputs at 1.25 Vdc. For example, if one input reaches 1.3 V, the common-mode circuit drives the other input to 1.2 V.
Ring Signal
CMPOUT
3.2.1 Linear Amplifier Gain
Display feature information (caller ID) and voice signals are coupled through the linear amplifier. In North America, CID data signals are typically sent between the first and second ringing signal burst. Referring to Figure 4, signal gain from tip and ring to LINOUT+ and LINOUT- is determined by:
3.3.2 Setting Ring Detection Threshold
The ring detection threshold depends on the component values of the input network. The values for these components shown in the typical application circuits are recommended for typical operation. Referring to Figure 4, the ring detection threshold can be changed according to the following formula:
750mV V RINGPK = ------------------- R RSNPD
2 1 ( 4R SNP + R SNPD ) + ------------------------------------2 ( f RING C SNP )
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CPC5710N
With the application circuit in Figure 4, the series capacitors serve to reduce the magnitude of highamplitude, low-frequency ring signals, making the ring detection threshold of the CPC5710N variable with the frequency the ringing signal. With the circuit as given, CMPOUT will change states with a 15 Hz ringing signal at approximately 48 VPEAK. For a 68 Hz ring signal, CMPOUT will change states with a ringing signal amplitude of approximately 11.5 VPEAK. In applications where CPC5710N will be used only as a ring level detector, or if significant attenuation of the amplified signal can be tolerated, the frequency variability of the ring detection threshold can be reduced by increasing the value of the resistors and capacitors in series with the input. Clare Application Note AN-117 Customize Caller ID Gain and Ring Detect Voltage Threshold is a spreadsheet for trying different component values in this circuit for LITELINK snoop circuit applications.
4. Power Quality
CPC5710N works best with a clean power supply. To clean up power supply noise, Clare, Inc., recommends using a pi network on the VDD pin as shown in Figure 7, if needed.
Figure 7. Optional Power Supply pi Network
3.3 or 5 V R100 10 C101 10 FB100 600 200 mA A
C100 1
A To VDD Pin 1
Note: For lower-frequency noise, use a 220 H inductor in series with R100.
5. Manufacturing Information
The CPC5710N branding (package imprinting) leaves off the last character of the part number due to package space limitations.
5.1 Package Dimensions
CPC5710N uses JEDEC standard 8-pin SOIC packaging. See JEDEC Publication 95, MS-012 for 3.75 (0.150) small-outline package dimensions.
5.2 Soldering
5.2.1 Moisture Reflow Sensitivity
Clare has characterized the moisture reflow sensitivity of this product using IPC/JEDEC standard J-STD020A and classifies it as MSL (Moisture Sensitivity Level) 1, not moisture sensitive.
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Rev. 1.0 12/16/2002
5.2.2 Reflow Profile
The maximum ramp rates, dwell times, and temperatures of the assembly reflow profile should not exceed those specified in IPC/JEDEC standard JSTD-020A, which were used to determine the moisture sensitivity level of this component.
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Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC5710N-R1.0 (c) Copyright 2002, Clare, Inc. All rights reserved. Printed in USA. 12/16/2002

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